There has been widely used, as a ROM (or mask ROM), the NOR-type ROM in which sources and drains of memory cells are formed with N-type conductive diffusion regions and word lines are arranged perpendicular to the diffusion regions. A circuit pattern with a matrix of memory cells in the N-type diffusion layers has been proposed in U.S. Pat. No. 5,268,861 by Y. Hotta et al and U.S. Pat. No. 5,349,563 by T. Iwase.
FIG. 1 shows Hotta's circuit configuration of a memory cell array in a ROM, and FIG. 2 is a plan view of the same memory cell array. In FIG. 1, the arrangement of bit lines is constructed of main bit lines MBL1.about.MBL4 and sub-bit lines SB1.about.SB8. Each of the odd-numbered main bit lines are connected to two of the odd-numbered sub-bit lines through two of the odd-numbered bank selection transistors BSO1.about.BSO4 in which gates of BSO1 and BSO3 are coupled to bank selection line BO1 and gates of BSO2 and BSO4 to BO2. Each of the even-numbered main bit lines are connected to two of the even-numbered sub-bit lines through two of even-numbered bank selection transistors BSE1.about.BSE4 in which gates of BSE1 and BSE3 are coupled to bank selection line BE1 and gates of BSE2 and BSE4 to BE2. And the odd-numbered main bit lines MBL1 and MBL3 are each coupled to sense amplifiers SA1 and SA2, and the even-numbered main bit lines MBL2 and MBL2 are connected to a ground potential each through transistors Q2 and Q3 gates of which are connected to control signal VS. Each of word lines WL1.about.WLn intersecting the bit lines is coupled to control gates of memory cells that are arranged in a row direction, while each of the sub-bit lines is coupled to adjacent memory cells.
In a read operation, assuming that M41 is on-cell and selected therein, BO1 and BE2 are set into a high potential while BO2 and BE1 are held in a low potential. WL1 goes to high level and VS is too high to switch Q2 on. Therefore, the current path for sensing is formed from MBL to the ground, through BSO3, SB5, M41, SB4, BSE2, MBL2 and Q2.
Referring FIG. 2, it is well known that the current path for sensing includes two regions 3 and 4 which are vertically formed of the diffusion layer, a gate oxide layer and the word line, as well as passing through the aforementioned positions. Such constructions of stray capacitances involved in the sensing current path cause the level of the sensing voltage to be reduced thereby, resulting in degrading an efficiency of the sensing operation. On the other hand, the sub-bit lines are formed by an N-conductive type diffusion layer, which is used for an active region of the bank selection transistor and determines channel width W of the bank selection transistor as shown in FIG. 2. The limit against the channel width of the bank selection transistor causes an increase of on-resistance (a resistance when the sensing current flows through an on cell) that reduces the amount of the sensing current for the on-cell.
Furthermore, the main bit line is connected to the active region of the bank selection transistor, at region 1 of the diffusion layer, through contact hole 2. With this construction, a junction capacitance between the main bit line and the region 2 and a gate capacitance of the bank selection transistor at the bit line badly influences the speed of data accessing.